1. Technical Field
The present disclosure relates to semiconductor integrated circuits, and more particularly, to a sense amplifier and a sense amplifier-based flip-flop having the same.
2. Discussion of Related Art
Mobile devices, such as cellular telephones, personal digital assistants (PDAs) and notebook computers, have an increased power management expense based on an increasingly large capacity and increasing clock speeds. Very large scale integration (VLSI) systems benefit from lower power consumption by improving their circuit structure or logic.
The circuit structure in the VLSI system may be largely divided into two functions. One function is a logic function to send a required output signal in response to an input signal, and the other one is a memory function to store an input signal in response to a clock signal or to output a stored signal. In a block having the latter function, the most fundamental and central portion may be a flip-flop.
As one example of the flip-flop, a sense amplifier-based flip-flop may be provided. The sense amplifier-based flip flop may be generally classified as a master latch and a slave latch.
As the master latch, a sense amplifier circuit of the current sensing type is mainly used, and a setup time of the master latch is very small, approximate to ‘0’. As the slave latch, a NAND type SR latch is mainly used, in which a very stabilized operation may be obtained with high clock speeds.
The master latch employs a dynamic structure, thus obtaining high clock speeds as a benefit of the dynamic structure. The slave latch employs a static structure, thus obtaining a stabilized operation as a benefit of the static structure.
FIG. 1 is a circuit diagram of a conventional sense amplifier-based flip-flop.
Referring to FIG. 1, the sense amplifier-based flip-flop may include a master latch 2 and a slave latch 1.
The master latch 2 includes four PMOS transistors PM1, PM2, PM3 and PM4, and five NMOS transistor NM1, NM2, NM3, NM4 and NM5. The slave latch 1 may be implemented with a NAND type SR latch (not shown).
In the master latch 2, a PMOS transistor PM1 is connected between a power terminal VDD and a first output node N1, and operates in response to a clock signal CLK. The first output node N1 and a second output node N2, to be described below, may be output terminals of the master latch 2 and also input terminals of the slave latch 1.
The PMOS transistor PM2 and the NMOS transistor NM1 and NM3 are disposed between the power terminal VDD and a drain terminal of an NMOS transistor NM5 connected to a fifth node N5. The NMOS transistor NM5 operates in response to the clock signal CLK.
Gate terminals of the PMOS transistor PM2 and the NMOS transistor NM1 are connected in common the second output node, N2, and an input signal D is applied to a gate terminal of the NMOS transistor NM3.
The PMOS transistor PM4 is disposed between the power terminal VDD and the second output node N2, and operates in response to the clock signal CLK.
The PMOS transistor PM3 and the NMOS transistors NM2 and NM4 are connected between the power terminal VDD and a drain terminal of the NMOS transistor NM5 connected to the fifth node N5.
Gate terminals of the PMOS transistor PM3 and the NMOS transistor NM2 are connected to the first output node N1, and an inverted input signal /D is applied to a gate terminal of the NMOS transistor NM4.
A conventional sense amplifier-based flip-flop having the master latch 2 and the slave latch 1 connected to the master latch 2 may be called a sense amplifier D flip-flop, since the sense amplifier-based flip-flop operates as a D flip-flop to receive applied input and inverted input signals D and /D and output delayed output and inverted delayed output signals Q and /Q in response to the clock signal CLK.
When the clock signal CLK has a low logic level, the first and second output nodes N1 and N2 become a high logic level regardless of the logic levels of the input and inverted input signals D and /D. In other words, when the clock signal CLK has a low logic level, the first output node N1 becomes a high logic level by a turn-on operation of the PMOS transistor PM1, and the second output node N2 becomes a high logic level by a turn-on operation of the PMOS transistor PM4.
At this time, the input signals S and R have a high logic level, thus output signals Q and /Q of the slave latch 1 are kept with their previous values intact, that is, a precharge state.
When the clock signal CLK becomes a high logic level, a voltage of output nodes N1 and N2 is decided by a logic state of the input signal D.
For example, if the clock signal CLK has a high logic level, and the input signal D has a high logic level, an output node N1 becomes a low logic level, and an output node N2 becomes a high logic level.
Meanwhile, the clock signal CLK becomes a high logic level, and the input signal D has a low logic level, the output node N1 becomes a high logic level and the output node N2 becomes a low logic level.
That is, when the clock signal CLK has a low logic level, output nodes N1 and N2 are precharged, and when the clock signal CLK has a high logic level, logic levels of the output nodes N1 and N2 are decided by an input signal D. A period provided when the clock signal CLK has a high logic level, may an evaluation period, and the master latch 2 has an evaluation state at the evaluation period. At this time, output signals of the output nodes N1 and n2 may be called evaluation signals.
In the sense amplifier-based flip-flop, in case a logic level of the input signal D is changed while the clock signal CLK is maintained as a high logic level, concerns may arise.
Referring to the following <TABLE 1>, the concerns will be described.
TABLE 1CLKD/DN1(S)N2(R)N3N4LXXHHHHHHLLHLFHLHFHFLLXXHHHHL indicates a low logic level, H indicates a high logic level, X indicates ‘don't care’, and F designates a floating.
The <TABLE 1> is a summary for operation of the sense amplifier-based flip-flop shown in FIG. 1, and FIG. 2 is a timing diagram illustrating operation of the conventional sense amplifier-based flip-flop of FIG. 1.
As shown in <TABLE 1> and in FIG. 2, if an input signal D is changed when clock signal CLK has a high logic level, output node N1 and node N3 have a low logic level, but the low logic level of a floating state. In other words, and NMOS transistor NM3 is turned off, thus the node N3 becomes floating, and so the output node N1 also becomes floating. The floating designates that a logic level of the output node N1 and node N3 may be easily changed by an external factor. This designates a state of the output node N1 and node N3 at a period t2. That is, the drawing shows that at the period t2, output nodes N1 and N2, and nodes N3 and N4, have a specific logic level, but such logic level may be easily changed by an external factor.
Further, in <TABLE 1>, only the case that the input signal D is changed from a high logic level to a logic level, was shown, but in case the input signal D is changed from a low logic level to a high logic level, the remaining ones except the output node N1 that is changed to an output node N2 and the node N3 is changed to a node N4, are the same.
The floating state causes unstable operation of the circuit or data loss.
FIG. 3 is a circuit diagram of an improved conventional sense amplifier-based flip-flop of FIG. 1.
Referring to FIG. 3, a sense amplifier-based flip-flop has an NMOS transistor NM16 to reduce floating at output nodes N11 and N12. FIG. 4 is a timing diagram illustrating operation of the improved conventional sense amplifier-based flip-flop of FIG. 3.
In FIG. 3, the configuration is the same as in the conventional sense amplifier-based flip-flop of FIG. 1, except for the addition of an NMOS transistor NM16 between a node N13 and a node N14 in a master latch 12, thus a repeated description will be omitted.
In the master latch 12, the NMOS transistor NM16 connected between node N13 and node N14 includes a gate terminal to which power source voltage VDD is always applied, and drain and source terminals connected to node N13 and node N14. The NMOS transistor NM16 maintains always a turn-on state in a circuit of the master latch 12.
The NMOS transistor NM16 has a relatively small driving capability as compared with NMOS transistors NM11, NM12, NM13, NM14 and NM15, since the NMOS transistor NM16 is always turned on to prevent a floating of node N11, N12 and so the NMOS transistor NM16 influences the master latch 12, that is, influences an evaluation operation of sense amplifier. In order to reduce such influence, the NMOS transistor NM16 has a relatively small driving capability.
In the sense amplifier-based flip-flop shown in FIG. 3, even though input signal D is changed, for example, from a high logic level to a low logic level or from a low logic level to a high logic level, in a high logic state of the clock signal CLK; output node N11, N12 or node N13, N14 of the sense amplifier-based flip-flop may be prevented from floating by an additional installation of the NMOS transistor NM16.
With reference to FIGS. 3 and 4, logic level change of output nodes N11 and N12 or nodes N13 and N14 will be described as follows.
For example, if clock signal CLK has a low logic level, PMOS transistor PM11, PM14 is turned on, and so output node N11, N12 and node N13, N14 maintain a high logic levels regardless of input signal D, /D. At this time, NMOS transistor NM11, NM12 is turned on and PMOS transistor PM12, PM13 is turned off.
If the clock signal CLK is transited to a high logic level, the PMOS transistor PM11, PM14 is turned off, and NMOS transistor NM15 is turned on. Herein, if input signal D has a high logic level, output node N11 becomes a low logic level, and output node N12 maintains a high logic level intact (A11). Also, NMOS transistor NM16 is always turned on, thus node N14 falls corresponding to a logic level of node N13 (A15).
In other words, a current path is formed along node N14, NMOS transistor NM16, node N13, NMOS transistor NM13, node N15 and NMOS transistor NM15, and after a lapse of given time, a logic level of the node N14 becomes the same as a logic level of the node N13 (actually, a threshold voltage of NMOS transistor NM16 should be considered, but from only the viewpoint of high or low logic level, it may be regarded as the same logic level).
Even if a logic level of the input signal is changed, maintaining a high logic level of the clock signal CLK, a logic level of the node N13, N14 is not changed, because the NMOS transistor NM16 is always turned on. Thus, a floating effect of output node N11, N12 shown in FIG. 1 is prevented.
This may be also applied equally to a case that a logic level to turn on the NMOS transistor NM13 by the input signal D is higher than a logic level to turn on the NMOS transistor NM14 by the input signal /D, instead of the case that the input signal D and the input signal /D have opposite logic levels.
For example, if the NMOS transistor NM13 is turned on with a relatively higher voltage level, the nodes N13 and N11 become a low logic level, and the nodes N12 and N14 maintain a high logic level. In this state, even in a case where logic level of the input signal D becomes a logic level by turning off the NMOS transistor NM13, occurs (of course, it should be a state that the NMOS transistor NM14 was turned on by the input signal /D); the node N13 does not become floating as the NMOS transistor NM16 has a turn-on state. Thus, the node N11 may be prevented from floating.
However, as shown in timings g1 and g2 of N13 and N14 shown in FIG. 4, a voltage difference between nodes N13 and N14, changed after the clock signal CLK is transited to a high logic level and in response to that, may be reduced substantially. Thus, a voltage difference between nodes N11 and N12 is reduced and an input sensitivity falls.
The input sensitivity means a capability of sense amplifier to sense and amplify a small voltage level difference between two signals, which is generally needed between the two signals in order to perform a sense operation of the sense amplifier.
In other words, the NMOS transistor NM16 is employed in the sense amplifier-based flip-flop, thus in an evaluation of the NMOS transistor NM16, a voltage difference between node N13 and node N14 is reduced, and there is a concern due to substantially decreasing the input sensitivity of the sense amplifier, causing errors in the operation of the sense amplifier-based flip-flop.
Consequently, a sense amplifier-based flip-flop without a floating output node as an output terminal of a master latch and without a drop of input sensitivity is desired.
FIG. 5 is a circuit diagram of a conventional sense amplifier-based flip-flop.
With reference to FIG. 5, the sense amplifier-based flip-flop includes a first latch 52 and a second latch 50.
The first latch 52 includes PMOS transistors PM51, PM52, PM53, PM54, PM55 and PM56, and NMOS transistors NM51, NM52, NM53, NM54 and NM55. The second latch 50 may be a general NAND type SR latch (not shown in detail).
The first latch 52 has a similar structure to the first latch 2 shown in FIG. 1.
The PMOS transistors PM15 and PM16 added to the first latch 2 of FIG. 1 are operationally connected with nodes N53 and N54 through the clock signal CLK, and provide power source voltage VDD to the nodes N53 and N54. The clock signal CLK is applied to gate terminals of the PMOS transistors PM55 and PM56. For example, when the clock signal CLK has a low logic level, the PMOS transistors PM55 and PM56 are turned on and provide power source voltage VDD to the nodes N53 and N54. If the clock signal CLK has a high logic level, the PMOS transistors PM55 and PM56 are turned off.
Operation of the sense amplifier-based flip-flop is similar to that of the sense amplifier shown in FIG. 1. A difference exists in that a voltage drop of the nodes N53 and N54 is reduced by the PMOS transistors PM55 and PM56.
FIG. 6 is a timing diagram illustrating operation of the conventional sense amplifier-based flip-flop of FIG. 5.
FIG. 6 illustrates waveforms based on timing of clock signal CLK, input signals D, /D, output nodes N51, N52, N53 and N54, and output signals Q, /Q.
When the clock signal has a low logic level, the output nodes N51, N52, N53 and N54 all maintain a high logic level.
When the clock signal is transited to a high logic level, a logic level of the output node N51, N52, N53, N54 is changed in response to the transition.
The logic level change of the output node N51, N52, N53, N54 based on the clock signal CLK and the input signals D, /D was described in full above.
FIG. 6 illustrates a delay time Td1 as a time from a transition of clock signal CLK to an applied time of output signal Q, /Q.
However, the conventional sense amplifier-based flip-flop has a precharge state during a low logic level of the clock signal CLK, and performs sense and amplification operation only during a high logic level of the clock signal CLK, thus it is difficult to reduce the delay time Td1 to a given length or below.
That is, in the conventional sense amplifier-based flip-flop shown in FIG. 4, a processing speed decreases due to a long delay time and it is difficult to design next-connected circuits.
Therefore a sense amplifier-based flip-flop circuit having a short delay time is necessarily required.
A bus channel in a system employing a memory device having the sense amplifier-based flip-flop circuit has a low pass filter characteristic, signals applied to the memory device frequently generate an inter symbol interference (ISI), which causes, for example, loss of data and error in the operation of the memory device.
As described above and with reference to FIGS. 1 to 6, the conventional sense amplifier-based flip-flop circuit has concerns, such as a floating situation, a drop of input sensitivity, a long delay time form a clock signal to an output signal, and an ISI situation of an input signal. The concerns frequently produce data loss and operational errors.
Therefore, a sense amplifier-based flip-flop resolving the concerns is desired.